1. Field of the Invention
The present invention relates to a video display device, more specifically to timing control of a sampling signal for a video signal based on a clock signal in a driving circuit of a video display device.
2. Description of Related Art
In recent years, there has been a strong commercial demand for video display devices, especially for use as monitors for devices such as a portable television and a mobile telephone. Further, display devices used for such a purpose have been actively researched and developed in attempts to satisfy the strong demand for display devices which are small, lightweight, and which consume less power.
FIG. 1 is an equivalent circuit diagram of a conventional liquid crystal display device, and FIG. 2 is a timing chart showing the driving of such a liquid crystal display device.
Referring to FIG. 1, a liquid crystal display panel P has the following structure. On an insulating substrate 10, a plurality of gate signal lines 51 connected to a gate driver 50 which supplies a gate signal, and a plurality of drain signal lines 61 are provided. A sampling transistor SPt1, SPt2 . . . SPtn turns on according to the timing of a sampling pulse output from a drain driver 60 which supplies a drain signal. In accordance with the actuation of the sampling transistor, a data signal (video signal) Sig is supplied from a video signal line 62 to the drain signal lines 61. Near each intersection of signal lines 51, 61, a TFT 70 is connected to the signal lines 51, 61 and a display electrode 80 is connected to the TFT 70.
Further, an LSI for driving the panel is provided on an external circuit substrate separately from the insulating substrate 10.
Clock signals CKH1 and CKH2 are supplied via external clock input sections T1 and T2, respectively, from the external panel driving LSI. These clock signals CKH1 and CKH2 are of opposite phases, and serve as a reference signal for generating a timing signal which determines the timing at which each of the sampling transistors SPt1, SPt2, SPt3 . . . latches a video signal.
Further, a start signal STV for a vertical driver and a start signal STH for a horizontal driver are also supplied from the panel driving LSI to the gate driver 50 and the drain driver 60, respectively. A data signal Sig is input to the video signal line 62.
The externally supplied clock signals, the external clock signals CKH1 and CKH2, are first input to level shifters (L/S), respectively, where the voltage of the signal is boosted from 0˜3 V to 0˜8 V, for example. The output signal is then input to a shaping inverter circuit 102, and is further input as a clock signal into each of shift registers which form the drain driver 60 via a buffer circuit 101.
Each shift register is composed of an inverter circuit and a clocked inverter circuit. A clock signal is sequentially passed to the next stage based on the horizontal direction start signal STH, so that each shift register generates a sampling pulse.
An externally input video signal is sampled by a sampling TFT based on the sampling pulse, and is then output to the corresponding drain signal line 61. More specifically, the sampling TFT SPt becomes ON in accordance with a sampling signal generated based on the start signal STH, and the video signal on the video signal line 62 is supplied to the drain signal line 61.
Further, the TFT 70 turns on when a gate signal is input from the gate signal line 51 to a gate electrode 13 thereof. This causes a drain signal to be applied to the display electrode 80 via the TFT 70. Simultaneously, a drain signal is also applied to a storage capacitor 85 via the TFT 70 so as to hold the voltage applied to the display electrode 80 for one field period. One electrode of the storage capacitor 85 is connected to the source 11s of the TFT 70 and to the other electrode a potential common for all the display pixels P11, P12, P13 . . . P21, P22, P23 . . . is applied.
The storage capacitor 85 is provided for the following reasons. When the gates 13 of the TFT 70 are opened so that the drain signal is applied to the liquid crystal 21, the voltage of the signal must be held for one field period. However, the voltage would be gradually lowered with time when only the liquid crystal 21 is provided, which results in flicker and unevenness in display thereby disenabling desirable display. The storage capacitor 85 is therefore provided to hold the voltage for one field period.
By supplying a voltage which has been applied to the display electrode 80 to the liquid crystal 21, the liquid crystal 21 orients in accordance with the applied voltage, thereby creating a display.
In conventional liquid crystal devices, however, the characteristics of each circuit, for example the inverter circuits 101, 102, may change due to variations in the manufacturing process conditions or the like. This further causes a change in the timing for sampling a video signal based on the clock signal. Namely, the sampling timing may sometimes be advanced or delayed.
As a result, the conventional liquid crystal display devices suffer from the following problems. Specifically, there is a possibility that a data signal is sampled by the sampling TFT SPt before the video signal line 62 is sufficiently charged to the potential of the video signal Sig, and the voltage of the sampled signal is supplied to each drain signal line 61. In such a case, an insufficient voltage is applied to the display electrode 80 which receives a drain signal from the drain line 61, and this disadvantageously degrades the display quality of the device.
FIG. 2 is a timing chart at points A, B, and C in FIG. 1.
As described above, a horizontal start signal STH is shifted within the drain driver 60 so that a sampling timing signal STH1, STH2 . . . is generated and output from each stage of the drain driver 60 (point A). These timing signals pass through various inverters so that they have the same phase but different polarities, and are then applied to the sampling TFT SPt1 (points B and C). However, when the timing signals for turning the sampling TFT SPt1 on are output, for example, at the timing as indicated in FIG. 2 (B, C) due to the characteristics change of the inverter circuit 101 or the like, the video signal S11 is sampled at timing where the potential of the video signal S11 is not yet established on the video signal line 62. In such a case, display quality is degraded.
One possible way of solving such a timing shift for sampling the video signal is to adjust the phases of the clock signals CKH1 and CKH2. More specifically, such phase adjustment refers to adjusting the delay time for the clock signals CKH1, CKH2, which can be achieved by changing the number of inverter circuits in the clock input section. However, because the inverter circuit cannot be changed once the various circuits have been formed, new pattern masks for the respective manufacturing processes must be further prepared for providing an additional inverter circuit. Specifically, it is necessary to additionally prepare all the pattern masks required at the various process steps for forming an inverter circuit including a process for forming an island shape active layer of the TFT through a process for forming the source and drain electrodes and the lines of the TFT. This method is disadvantageous in that for the cost of creating such additional pattern masks is great.